The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2012
Filed:
Jan. 31, 2011
Ki-ha Hong, Cheonan-si, KR;
U-in Chung, Seoul, KR;
Jai-kwang Shin, Anyang-si, KR;
Jae-joon OH, Seongnam-si, KR;
Jong-seob Kim, Hwaseong-si, KR;
Hyuk-soon Choi, Hwaseong-si, KR;
In-jun Hwang, Hwaseong-si, KR;
Ki-ha Hong, Cheonan-si, KR;
U-In Chung, Seoul, KR;
Jai-kwang Shin, Anyang-si, KR;
Jae-joon Oh, Seongnam-si, KR;
Jong-seob Kim, Hwaseong-si, KR;
Hyuk-soon Choi, Hwaseong-si, KR;
In-jun Hwang, Hwaseong-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
A method of manufacturing a High Electron Mobility Transistor (HEMT) may include forming first and second material layers having different lattice constants on a substrate, forming a source, a drain, and a gate on the second material layer, and changing the second material layer between the gate and the drain into a different material layer, or changing a thickness of the second material layer, or forming a p-type semiconductor layer on the second material layer. The change in the second material layer may occur in an entire region of the second material layer between the gate and the drain, or only in a partial region of the second material layer adjacent to the gate. The p-type semiconductor layer may be formed on an entire top surface of the second material layer between the gate and the drain, or only on a partial region of the top surface adjacent to the gate.