The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2012
Filed:
May. 03, 2010
Ching-te Chuang, Taipei, TW;
Hao-i Yang, Taipei, TW;
Jihi-yu Lin, Kaohsiung County, TW;
Shyh-chyi Yang, Taipei County, TW;
Ming-hsien Tu, Tainan, TW;
Wei Hwang, Taipei, TW;
Shyh-jye Jou, Hsinchu County, TW;
Kun-ti Lee, Hsinchu County, TW;
Hung-yu LI, Pingtung County, TW;
Ching-Te Chuang, Taipei, TW;
Hao-I Yang, Taipei, TW;
Jihi-Yu Lin, Kaohsiung County, TW;
Shyh-Chyi Yang, Taipei County, TW;
Ming-Hsien Tu, Tainan, TW;
Wei Hwang, Taipei, TW;
Shyh-Jye Jou, Hsinchu County, TW;
Kun-Ti Lee, Hsinchu County, TW;
Hung-Yu Li, Pingtung County, TW;
Faraday Technology Corp., Science-Based Industrial Park, Hsin-Chu, TW;
National Chiao Tung University, Hsinchu, TW;
Abstract
A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.