The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2012
Filed:
Jan. 07, 2010
Anthony I. Chou, Hopewell Junction, NY (US);
Arvind Kumar, Hopewell Junction, NY (US);
Shreesh Narasimha, Hopewell Junction, NY (US);
Ning Su, Hopewell Junction, NY (US);
Huiling Shang, Hopewell Junction, NY (US);
Anthony I. Chou, Hopewell Junction, NY (US);
Arvind Kumar, Hopewell Junction, NY (US);
Shreesh Narasimha, Hopewell Junction, NY (US);
Ning Su, Hopewell Junction, NY (US);
Huiling Shang, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.