The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2012
Filed:
Dec. 16, 2010
Hideaki Sakaguchi, Nagano, JP;
Mitsutoshi Higashi, Nagano, JP;
Yuichi Taguchi, Nagano, JP;
Akinori Shiraishi, Nagano, JP;
Kei Murayama, Nagano, JP;
Hideaki Sakaguchi, Nagano, JP;
Mitsutoshi Higashi, Nagano, JP;
Yuichi Taguchi, Nagano, JP;
Akinori Shiraishi, Nagano, JP;
Kei Murayama, Nagano, JP;
Shinko Electric Industries Co., Ltd., Nagano-shi, JP;
Abstract
There is provided a method of manufacturing a semiconductor package. The method includes: (a) providing a silicon wafer comprising a first surface and a second surface opposite to the first surface; (b) forming vias through the silicon wafer in its thickness direction; (c) forming wiring patterns on the first surface of the silicon wafer such that the wiring patterns are electrically connected to the vias; (d) bonding a MEMS element wafer comprising MEMS elements onto the second surface of the silicon wafer such that the MEMS elements are electrically connected to the vias; (e) dividing the MEMS element wafer into the respective MEMS elements; (f) bonding a lid having concave portions therein onto the second surface of the silicon wafer such that the respective MEMS elements face a corresponding one of the concave portions; and (g) dicing the lid and the silicon wafer.