The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2012
Filed:
Aug. 27, 2009
Andreas Goebel, Mountain View, CA (US);
Paul A. Clifton, Mountain View, CA (US);
Daniel J. Connelly, San Francisco, CA (US);
Vaishali Ukirde, San Jose, CA (US);
Andreas Goebel, Mountain View, CA (US);
Paul A. Clifton, Mountain View, CA (US);
Daniel J. Connelly, San Francisco, CA (US);
Vaishali Ukirde, San Jose, CA (US);
Acorn Technologies, Inc., Santa Monica, CA (US);
Abstract
FET configurations in which two (or more) facets are exposed on a surface of a semiconductor channel, the facets being angled with respect to the direction of the channel, allow for conformal deposition of a convex or concave S/D. A convex tip of the S/D enhances electric fields at the interface, reducing the resistance between the S/D and the channel. In contrast, a S/D having a concave tip yields a dual-gate FET that emphasizes reduced short-channel effects rather than electric field enhancement. The use of self-limiting, selective wet etches to expose the facets facilitates process control, control of interface chemistry, and manufacturability.