The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2012
Filed:
Aug. 10, 2009
Bang-chiang Lan, Taipei, TW;
Ming-i Wang, Taipei County, TW;
Hui-min Wu, Hsinchu County, TW;
Min Chen, Taipei County, TW;
Chien-hsin Huang, Taichung, TW;
Tzung-i Su, Yun-Lin County, TW;
Chao-an Su, Kaohsiung County, TW;
Tzung-han Tan, Taipei, TW;
Li-che Chen, Ping-Tung, TW;
Meng-jia Lin, Changhua County, TW;
Bang-Chiang Lan, Taipei, TW;
Ming-I Wang, Taipei County, TW;
Hui-Min Wu, Hsinchu County, TW;
Min Chen, Taipei County, TW;
Chien-Hsin Huang, Taichung, TW;
Tzung-I Su, Yun-Lin County, TW;
Chao-An Su, Kaohsiung County, TW;
Tzung-Han Tan, Taipei, TW;
Li-Che Chen, Ping-Tung, TW;
Meng-Jia Lin, Changhua County, TW;
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which encompasses the connection region. The protection structure includes at least a barrier, an insulation layer and a mask layer. The barrier is disposed in the dielectric layer in the peripheral region. The insulation layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulation layer and the mask layer includes an opening to expose the connection region of the pad.