The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 22, 2012
Filed:
Jul. 02, 2010
Chien-ping Huang, Taichung, TW;
Chih-ming Huang, Taichung, TW;
Han-ping Pu, Taichung, TW;
Yu-po Wang, Taichung, TW;
Cheng-hsu Hsiao, Taichung, TW;
Chien-Ping Huang, Taichung, TW;
Chih-Ming Huang, Taichung, TW;
Han-Ping Pu, Taichung, TW;
Yu-Po Wang, Taichung, TW;
Cheng-Hsu Hsiao, Taichung, TW;
Siliconware Precision Industries Co., Ltd., Taichung, TW;
Abstract
A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.