The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2012

Filed:

Dec. 13, 2006
Applicants:

Ryosuke Ishii, Osaka, JP;

Koji Nakayama, Osaka, JP;

Yoshitaka Sugawara, Osaka, JP;

Toshiyuki Miyanagi, Yokosuka, JP;

Hidekazu Tsuchida, Yokosuka, JP;

Isaho Kamata, Yokosuka, JP;

Tomonori Nakamura, Yokosuka, JP;

Inventors:

Ryosuke Ishii, Osaka, JP;

Koji Nakayama, Osaka, JP;

Yoshitaka Sugawara, Osaka, JP;

Toshiyuki Miyanagi, Yokosuka, JP;

Hidekazu Tsuchida, Yokosuka, JP;

Isaho Kamata, Yokosuka, JP;

Tomonori Nakamura, Yokosuka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/15 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a SiC bipolar semiconductor device with a mesa structure having a SiC drift layer of a first conductive type and a SiC carrier injection layer of a second conductive type that are SiC epitaxial layers grown from a surface of a SiC single crystal substrate, the formation of stacking faults and the expansion of the area thereof are prevented and thereby the increase in forward voltage is prevented. Further, a characteristic of withstand voltage in a reverse biasing is improved. An forward-operation degradation preventing layer is formed on a mesa wall or on a mesa wall and a mesa periphery to separate spatially the surface of the mesa wall from a pn-junction interface. In one embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide low resistance layer of a second conductive type that is equipotential during the application of a reverse voltage. In another embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide conductive layer of a second conductive type, and a metal layer that is equipotential during the application of a reverse voltage is formed on a surface of the silicon carbide conductive layer. In still another embodiment, the forward-operation degradation preventing layer is composed of a high resistance amorphous layer.


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