The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2012
Filed:
Aug. 07, 2008
Wanda Andreoni, Adliswil, CH;
Alessandro C. Callegari, Yorktown Heights, NY (US);
Eduard A. Cartier, New York, NY (US);
Alessandro Curioni, Gattikon, CH;
Christopher P. D'emic, Ossining, NY (US);
Evgeni Gousev, Mahopac, NY (US);
Michael A. Gribelyuk, Stamford, CT (US);
Paul C. Jamison, Hopewell Junction, NY (US);
Rajarao Jammy, Hopewell Junction, NY (US);
Dianne L. Lacey, Mahopac, NY (US);
Fenton R. Mcfeely, Ossining, NY (US);
Vijay Narayanan, New York, NY (US);
Carlo A. Pignedoli, Adliswil, CH;
Joseph F. Shepard, Jr., Fishkill, NY (US);
Sufi Zafar, Briarcliff Manor, NY (US);
Wanda Andreoni, Adliswil, CH;
Alessandro C. Callegari, Yorktown Heights, NY (US);
Eduard A. Cartier, New York, NY (US);
Alessandro Curioni, Gattikon, CH;
Christopher P. D'Emic, Ossining, NY (US);
Evgeni Gousev, Mahopac, NY (US);
Michael A. Gribelyuk, Stamford, CT (US);
Paul C. Jamison, Hopewell Junction, NY (US);
Rajarao Jammy, Hopewell Junction, NY (US);
Dianne L. Lacey, Mahopac, NY (US);
Fenton R. McFeely, Ossining, NY (US);
Vijay Narayanan, New York, NY (US);
Carlo A. Pignedoli, Adliswil, CH;
Joseph F. Shepard, Jr., Fishkill, NY (US);
Sufi Zafar, Briarcliff Manor, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×10charges/cmor less, a peak mobility of about 250 cmV-s or greater and substantially no mobility degradation at about 6.0×10inversion charges/cmor greater.