The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2012
Filed:
Dec. 14, 2010
Brian S. Doyle, Portland, OR (US);
Robert S. Chau, Beaverton, OR (US);
Suman Datta, Beaverton, OR (US);
Vivek DE, Beaverton, OR (US);
Ali Keshavarzi, Portland, OR (US);
Dinesh Somasekhar, Portland, OR (US);
Brian S. Doyle, Portland, OR (US);
Robert S. Chau, Beaverton, OR (US);
Suman Datta, Beaverton, OR (US);
Vivek De, Beaverton, OR (US);
Ali Keshavarzi, Portland, OR (US);
Dinesh Somasekhar, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A capacitor includes a substrate (), a first electrically insulating layer () over the substrate, and a fin () including a semiconducting material () over the first electrically insulating layer. A first electrically conducting layer () is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer () is located adjacent to the first electrically conducting layer, and a second electrically conducting layer () is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.