The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2012
Filed:
Aug. 15, 2008
Chien-wen Chen, Kaohsiung, TW;
Yi-shao Lai, Yonghe, TW;
Hsiao-chuan Chang, Kaohsiung, TW;
Tsung-yueh Tsai, Gangshan Township, TW;
Pao-huei Chang Chien, Fongshan, TW;
Ping-cheng HU, Kaohsiung, TW;
Hsu-yang Lee, Tainan, TW;
Chien-Wen Chen, Kaohsiung, TW;
Yi-Shao Lai, Yonghe, TW;
Hsiao-Chuan Chang, Kaohsiung, TW;
Tsung-Yueh Tsai, Gangshan Township, TW;
Pao-Huei Chang Chien, Fongshan, TW;
Ping-Cheng Hu, Kaohsiung, TW;
Hsu-Yang Lee, Tainan, TW;
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
Abstract
A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.