The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8053317 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 08, 2011

Filed:

Aug. 15, 2009
Applicants:

Satya N. Chakravarti, Hopewell Junction, NY (US);

Dechao Guo, Wappingers Falls, NY (US);

Wilfried Ernst-august Haensch, Somers, NY (US);

Pranita Kulkarni, Albany, NY (US);

Fei Liu, Mt. Kisco, NY (US);

Philip J. Oldiges, Lagrangeville, NY (US);

Keith Kwong Hon Wong, Wappingers Falls, NY (US);

Inventors:

Satya N. Chakravarti, Hopewell Junction, NY (US);

Dechao Guo, Wappingers Falls, NY (US);

Wilfried Ernst-August Haensch, Somers, NY (US);

Pranita Kulkarni, Albany, NY (US);

Fei Liu, Mt. Kisco, NY (US);

Philip J. Oldiges, Lagrangeville, NY (US);

Keith Kwong Hon Wong, Wappingers Falls, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
Abstract

Method of forming a semiconductor device which includes the steps of obtaining a semiconductor substrate having a logic region and an STI region; sequentially depositing layers of high K material, metal gate, first silicon and hardmask; removing the hardmask and first silicon layers from the logic region; applying a second layer of silicon on the semiconductor substrate such that the logic region has layers of high K material, metal gate and second silicon and the STI region has layers of high K material, metal gate, first silicon, hardmask and second silicon. There may also be a second hardmask layer between the metal gate layer and the first silicon layer in the STI region. There may also be a hardmask layer between the metal gate layer and the first silicon layer in the STI region but no hardmask layer between the first and second layers of silicon in the STI region.


Find Patent Forward Citations

Chakravarti, Satya. (2011). Method and structure for improving uniformity of passive devices in metal gate technology (U.S. Patent No. 8053317). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8053317

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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