The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 2011
Filed:
Dec. 31, 2008
Young Hy Jung, Gyeonggi-do, KR;
Jae Sung OH, Gyeonggi-do, KR;
Ki IL Moon, Gyeonggi-do, KR;
Ki Chae Kim, Seoul, KR;
Chan Sun Lee, Seoul, KR;
Jin Ho Gwon, Gyeonggi-do, KR;
Jae Youn Choi, Gyeonggi-do, KR;
Young Hy Jung, Gyeonggi-do, KR;
Jae Sung Oh, Gyeonggi-do, KR;
Ki Il Moon, Gyeonggi-do, KR;
Ki Chae Kim, Seoul, KR;
Chan Sun Lee, Seoul, KR;
Jin Ho Gwon, Gyeonggi-do, KR;
Jae Youn Choi, Gyeonggi-do, KR;
Hynix Semiconductor Inc., Gyeonggi-do, KR;
Abstract
A substrate for a semiconductor package having a reinforcing member that prevents or minimizes distortions is presented. The substrate for the semiconductor package includes a substrate body, an insulation layer, and a reinforcing member. The substrate body has a first region having a plurality of chip mount regions, a second region disposed along a periphery of the first region, a circuit pattern disposed in each chip mount region and a dummy pattern disposed along the second region. The insulation layer covers the first and second regions and has an opening exposing some portion of each circuit pattern. The reinforcing member is disposed in the second region and prevents deflection of the substrate body.