The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2011
Filed:
Jun. 29, 2009
Gregory G. Freeman, Hopewell Junction, NY (US);
Shreesh Narasimha, Hopewell Junction, NY (US);
Ning Su, Hopewell Junction, NY (US);
Hasan M. Nayfeh, Hopewell Junction, NY (US);
Nivo Rovedo, Hopewell Junction, NY (US);
Werner A. Rausch, Hopewell Junction, NY (US);
Jian Yu, Hopewell Junction, NY (US);
Gregory G. Freeman, Hopewell Junction, NY (US);
Shreesh Narasimha, Hopewell Junction, NY (US);
Ning Su, Hopewell Junction, NY (US);
Hasan M. Nayfeh, Hopewell Junction, NY (US);
Nivo Rovedo, Hopewell Junction, NY (US);
Werner A. Rausch, Hopewell Junction, NY (US);
Jian Yu, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.