The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2011

Filed:

Dec. 29, 2006
Applicants:

Koo Hong Lee, Seoul, KR;

IL Kwon Shim, Singapore, SG;

Young Cheol Kim, Yongin-si, KR;

Bongsuk Choi, Kyoungki-do, KR;

Inventors:

Koo Hong Lee, Seoul, KR;

Il Kwon Shim, Singapore, SG;

Young Cheol Kim, Yongin-si, KR;

Bongsuk Choi, Kyoungki-do, KR;

Assignee:

Stats Chippac Ltd, Singapore, SG;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

A wafer level chip scale package system is provided including placing a first integrated circuit over a semiconductor wafer having a second integrated circuit; connecting a second electrical interconnect between the first integrated circuit and the second integrated circuit; forming a stress relieving encapsulant on the outer perimeter of the second integrated circuit for covering the second electrical interconnect; and singulating a chip scale package, from the semiconductor wafer, through the stress relieving encapsulant and the semiconductor wafer.


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