The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2011
Filed:
Jul. 10, 2009
David Wei Wang, Hsinchu, TW;
An-hong Liu, Hsinchu, TW;
Hao-yin Tsai, Hsinchu, TW;
Hsiang-ming Huang, Hsinchu, TW;
Yi-chang Lee, Hsinchu, TW;
Shu-ching Ho, Hsinchu, TW;
David Wei Wang, Hsinchu, TW;
An-Hong Liu, Hsinchu, TW;
Hao-Yin Tsai, Hsinchu, TW;
Hsiang-Ming Huang, Hsinchu, TW;
Yi-Chang Lee, Hsinchu, TW;
Shu-Ching Ho, Hsinchu, TW;
Chipmos Technologies Inc., Hsinchu, TW;
Abstract
Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.