The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2011
Filed:
May. 30, 2008
Xiaoqing Wen, Fukuoka, JP;
Seiji Kajihara, Fukuoka, JP;
Kohei Miyase, Fukuoka, JP;
Yoshihiro Minamoto, Fukuoka, JP;
Hiroshi Date, Fukuoka, JP;
Xiaoqing Wen, Fukuoka, JP;
Seiji Kajihara, Fukuoka, JP;
Kohei Miyase, Fukuoka, JP;
Yoshihiro Minamoto, Fukuoka, JP;
Hiroshi Date, Fukuoka, JP;
Japan Science & Technology Agency, Saitama, JP;
Kyushu Institute of Technology, Fukuoka, JP;
System JD Co., Ltd., Fukuoka, JP;
Abstract
Provided are a conversion device and others for converting a test vector set so as to reduce a logic value difference generated before and after scan capture in outputs of scan cells included in a full scan sequential circuit. A conversion device converts a test vector set corresponding to the full scan sequential circuit. The conversion device comprises a setting unit for setting a candidate bit which can be a don't care bit and a fixed bit which cannot be the don't care bit according to predetermined constraint conditions based on an input-output relationship in the logic circuit in order to identify the don't care bit identifiable as don't care from each test vector of the test vector set, and a logic value deciding unit for deciding a logic value for the don't care bit in view of a relationship in a plurality of bit pairs in relation to a test cube including the don't care bit identified by the setting unit.