Generating device, generating method, program and recording medium

Abstract

A generation apparatus and the like for generating a test vector set capable of reducing differences in a logic value generated before and after a scan capture for outputs from scan cells included in a full-scan sequential circuit are provided. A generation apparatusgenerating an initial test vector setfor a logic circuit includes a target vector identification unitidentifying a test vector satisfying a predetermined criterion and to be selected for the number of bits (the number of bit transitions) whose logic values differ before and after scan capture with respect to outputs from scan cells included in the sequential circuit, from among test vectors in the initial test vector set, and a test vector set conversion unitconverting the test vector identified by the test vector identification unitand to be selected so as to reduce the number of bit transitions with respect to outputs from the scan cells included in the sequential circuit.