The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2011
Filed:
Nov. 13, 2009
Zhijiong Luo, Carmel, NY (US);
Ricky S. Amos, Rhinebeck, NY (US);
Nivo Rovedo, LaGrangeville, NY (US);
Henry K. Utomo, Newburgh, NY (US);
Zhijiong Luo, Carmel, NY (US);
Ricky S. Amos, Rhinebeck, NY (US);
Nivo Rovedo, LaGrangeville, NY (US);
Henry K. Utomo, Newburgh, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.