The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2011

Filed:

Sep. 07, 2006
Applicants:

Takaharu Yamano, Nagano, JP;

Kosaku Harayama, Nagano, JP;

Hiroyuki Kato, Nagano, JP;

Tetsuya Koyama, Nagano, JP;

Inventors:

Takaharu Yamano, Nagano, JP;

Kosaku Harayama, Nagano, JP;

Hiroyuki Kato, Nagano, JP;

Tetsuya Koyama, Nagano, JP;

Assignee:

Shinko Electric Industries Co., Ltd., Nagano-shi, Nagano, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B29C 65/00 (2006.01); A41G 1/00 (2006.01); B32B 37/00 (2006.01); C23F 3/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The method for forming wiring includes: laminating a thermosetting resin film and a metallic foil on an insulating substrate where base-layer wiring is formed, a mat surface of the metallic foil facing the resin film, pressing the film and the foil with application of heat; forming an opening in the metallic foil to expose a part of the insulating resin layer in which a via hole is to be formed; forming the via hole in the insulating resin layer by using as a mask the metallic foil; performing a desmear process of the via hole via the opening of the metallic foil; removing the metallic foil; forming an electroless-plated layer that covers the top surface of the insulating resin layer, a side surface of the via hole and a top surface of the base-layer wiring; and forming wiring including an electroplated layer on the electroless-plated layer.


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