The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 2011
Filed:
Jan. 28, 2004
Lingyi A. Zheng, Boise, ID (US);
Trung T. Doan, Pflugerville, TX (US);
Lyle D. Breiner, Meridian, ID (US);
Er-xuan Ping, Meridian, ID (US);
Kevin L. Beaman, Boise, ID (US);
Ronald A. Weimer, Boise, ID (US);
Cem Basceri, Boise, ID (US);
David J. Kubista, Nampa, ID (US);
Lingyi A. Zheng, Boise, ID (US);
Trung T. Doan, Pflugerville, TX (US);
Lyle D. Breiner, Meridian, ID (US);
Er-Xuan Ping, Meridian, ID (US);
Kevin L. Beaman, Boise, ID (US);
Ronald A. Weimer, Boise, ID (US);
Cem Basceri, Boise, ID (US);
David J. Kubista, Nampa, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 Å.