The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2011

Filed:

Mar. 23, 2007
Applicants:

Chung-chi Ko, Nantou, TW;

Lih-ping LI, Hsinchu, TW;

Yung-cheng LU, Taipei, TW;

Hui-lin Chang, Hsinchu, TW;

Chih-hsien Lin, Tainan, TW;

Inventors:

Chung-Chi Ko, Nantou, TW;

Lih-Ping Li, Hsinchu, TW;

Yung-Cheng Lu, Taipei, TW;

Hui-Lin Chang, Hsinchu, TW;

Chih-Hsien Lin, Tainan, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging.


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