The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2011

Filed:

Mar. 25, 2008
Applicants:

Byung Joon Han, Singapore, SG;

Nathapong Suthiwongsunthorn, Singapore, SG;

Pandi Chelvam Marimuthu, Singapore, SG;

Kock Liang Heng, Singapore, SG;

Inventors:

Byung Joon Han, Singapore, SG;

Nathapong Suthiwongsunthorn, Singapore, SG;

Pandi Chelvam Marimuthu, Singapore, SG;

Kock Liang Heng, Singapore, SG;

Assignee:

STATS ChipPAC, Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer exposing the conductive layer, a second via formed in the carrier wafer exposing the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second passivation layers are deposited over the first and second metal layers. The first or second passivation layer has an etched portion to expose a portion of the first metal layer or second metal layer.


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