The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 2011
Filed:
Feb. 14, 2006
Shinya Sadohara, Omura, JP;
Ryota Suewaka, Omura, JP;
Shiro Yoshino, Omura, JP;
Kozo Nakamura, Omura, JP;
Yutaka Shiraishi, Omura, JP;
Syunji Nonaka, Omura, JP;
Shinya Sadohara, Omura, JP;
Ryota Suewaka, Omura, JP;
Shiro Yoshino, Omura, JP;
Kozo Nakamura, Omura, JP;
Yutaka Shiraishi, Omura, JP;
Syunji Nonaka, Omura, JP;
Sumco Techxiv Corporation, Nagasaki, JP;
Abstract
A method in which SSDs are reliably reduced while reducing void defects other than the SSDs on a wafer surface, which is essential for an annealed wafer, and ensuring that BMDs serving as gettering source in a bulk are generated, in order to stabilize the quality of the annealed wafer. Considering that annealing a silicon wafer leads to an increase of density (quantity) of deposits associated with oxygen and nitrogen and forming a core of the SSDs, SSDs are decreased by reducing the density (quantity) of the deposits associated with oxygen and nitrogen by controlling three parameters of oxygen concentration, nitrogen concentration and cooling concentration during the process of pulling and growing the silicon single crystalbefore annealing. Alternatively, SSD is reduced by polishing after annealing.