The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 23, 2010
Filed:
Jan. 26, 2009
Unoh Kwon, Fishkill, NY (US);
Siddarth A. Krishnan, Peekskill, NY (US);
Takashi Ando, Tuckahoe, NY (US);
Michael P. Chudzik, Danbury, CT (US);
Martin M. Frank, Dobbs Ferry, NY (US);
William K. Henson, Beacon, NY (US);
Rashmi Jha, Toledo, OH (US);
Yue Liang, Beacon, NY (US);
Vijay Narayanan, New York, NY (US);
Ravikumar Ramachandran, Pleasantville, NY (US);
Keith Kwong Hon Wong, Wappingers Falls, NY (US);
Unoh Kwon, Fishkill, NY (US);
Siddarth A. Krishnan, Peekskill, NY (US);
Takashi Ando, Tuckahoe, NY (US);
Michael P. Chudzik, Danbury, CT (US);
Martin M. Frank, Dobbs Ferry, NY (US);
William K. Henson, Beacon, NY (US);
Rashmi Jha, Toledo, OH (US);
Yue Liang, Beacon, NY (US);
Vijay Narayanan, New York, NY (US);
Ravikumar Ramachandran, Pleasantville, NY (US);
Keith Kwong Hon Wong, Wappingers Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiOand alpha-silicon layers or a dBARC layer.