The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 23, 2010
Filed:
Jul. 03, 2007
Tjandra Winata Karta, Hsinchu, TW;
Steven Hsu, Chung-Ho, TW;
Chien-hsiun Lee, Hsin-Chu, TW;
Gene Wu, Dayuan Township, TW;
Jimmy Liang, Chung-Li, TW;
Tjandra Winata Karta, Hsinchu, TW;
Steven Hsu, Chung-Ho, TW;
Chien-Hsiun Lee, Hsin-Chu, TW;
Gene Wu, Dayuan Township, TW;
Jimmy Liang, Chung-Li, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
An improved Wafer-Level Chip-Scale Packaging (WLCSP) process is described that includes forming a plurality of conductive pillars on a first surface of a semiconductor wafer. One or more grooves are dry etched into the first surface of the semiconductor wafer, where the grooves define at least one boundary between each of a plurality of die within the semiconductor wafer. A layer of encapsulating material is deposited over the first surface. A recess is then cut in each of the grooves through the encapsulating material, where the cutting leaves a piece of semiconductor material on the second surface of the semiconductor wafer. The second surface is then ground to remove the piece of semiconductor material, where the removal of this material separates the plurality of die.