The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 12, 2010
Filed:
Jun. 28, 2007
Anthony I. Chou, Beacon, NY (US);
James S. Dunn, Jericho, VT (US);
Brian M. Dufrene, Grand Isle, VT (US);
Christopher H. Lumbra, Essex Junction, VT (US);
Shreesh Narasimha, Beacon, NY (US);
Christopher S. Putnam, Hinesburg, VT (US);
Bethann Rainey, Williston, VT (US);
Christopher M. Schnabel, Poughkeepsie, NY (US);
Anthony I. Chou, Beacon, NY (US);
James S. Dunn, Jericho, VT (US);
Brian M. Dufrene, Grand Isle, VT (US);
Christopher H. Lumbra, Essex Junction, VT (US);
Shreesh Narasimha, Beacon, NY (US);
Christopher S. Putnam, Hinesburg, VT (US);
BethAnn Rainey, Williston, VT (US);
Christopher M. Schnabel, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system, method and program product that allows multiple devices to be placed between pads such that a Back End Of Line (BEOL) mask change can be used to select different device options. A system is disclosed for implementing a testsite for characterizing devices in an integrated circuit technology, and includes: a system for designing a plurality of device options for a set of chip pads; a system for designing a pseudo wiring layout for each of the plurality of device options; a system for selecting one of the device options; a system for mapping the pseudo wiring layout for a selected device option to a predetermined design level; and a system for outputting a configured mask design at the predetermined design level having a wiring layout mapped for the selected device option.