The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2010

Filed:

Oct. 13, 2008
Applicants:

Anand Murthy, Portland, OR (US);

Glenn A. Glass, Beaverton, OR (US);

Andrew N. Westmeyer, Beaverton, OR (US);

Michael L. Hattendorf, Beaverton, OR (US);

Jeffrey R. Wank, Tigard, OR (US);

Inventors:

Anand Murthy, Portland, OR (US);

Glenn A. Glass, Beaverton, OR (US);

Andrew N. Westmeyer, Beaverton, OR (US);

Michael L. Hattendorf, Beaverton, OR (US);

Jeffrey R. Wank, Tigard, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/119 (2006.01);
U.S. Cl.
CPC ...
Abstract

This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.


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