The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2010
Filed:
Jan. 04, 2007
Mei-yun Wang, Hsinchu, TW;
Cheng-chen Hsueh, Taipei, TW;
Wu-an Weng, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, Taiwan, CN;
Abstract
Semiconductor devices with selective stress memory effect and fabrication methods thereof. The semiconductor device comprises a semiconductor substrate with a first region and a second region. Both the first region and the second region have a first doped region and a second doped region separated by an insulation layer. A PMOS transistor is disposed on the first doped region layer. An NMOS transistor is disposed on the second doped region. A first capping layer is disposed covering the NMOS transistor over the first region. A second capping layer is disposed covering the PMOS transistor over the first region. The thickness of the first capping layer is different from the thickness of the second capping layer, thereby different stress is induced on the PMOS transistor and the NMOS transistor respectively. The PMOS transistor and the NMOS transistor over the second region are silicided.