The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 2010
Filed:
Jan. 09, 2006
John C. Arnold, Ridgefield, CT (US);
Dureseti Chidambarrao, Weston, CT (US);
Ying LI, Newburgh, NY (US);
Rajeev Malik, Pleasantville, NY (US);
Shreesh Narasimha, Beacon, NY (US);
Siddhartha Panda, Beacon, NY (US);
Brian L. Tessier, Poughkeepsie, NY (US);
Richard Wise, New Windsor, NY (US);
John C. Arnold, Ridgefield, CT (US);
Dureseti Chidambarrao, Weston, CT (US);
Ying Li, Newburgh, NY (US);
Rajeev Malik, Pleasantville, NY (US);
Shreesh Narasimha, Beacon, NY (US);
Siddhartha Panda, Beacon, NY (US);
Brian L. Tessier, Poughkeepsie, NY (US);
Richard Wise, New Windsor, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.