The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2010

Filed:

Jan. 02, 2009
Applicants:

Kamalesh K. Srivastava, Wappingers Falls, NY (US);

Subhash L. Shinde, Courtlandt Manor, NY (US);

Tien-jen Cheng, Beford, NY (US);

Sarah H. Knickerbocker, Hopewell Junction, NY (US);

Roger A. Quinn, Rhinebeck, NY (US);

William E. Sablinski, Beacon, NY (US);

Julie C. Biggs, Wappingers Falls, NY (US);

David E. Eichstadt, Park Ridge, IL (US);

Jonathan H. Griffith, Lagrangeville, NY (US);

Inventors:

Kamalesh K. Srivastava, Wappingers Falls, NY (US);

Subhash L. Shinde, Courtlandt Manor, NY (US);

Tien-Jen Cheng, Beford, NY (US);

Sarah H. Knickerbocker, Hopewell Junction, NY (US);

Roger A. Quinn, Rhinebeck, NY (US);

William E. Sablinski, Beacon, NY (US);

Julie C. Biggs, Wappingers Falls, NY (US);

David E. Eichstadt, Park Ridge, IL (US);

Jonathan H. Griffith, Lagrangeville, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.


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