Methods for fabricating improved gate dielectrics

Abstract

Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.