The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 13, 2010
Filed:
Jun. 20, 2007
Masaru Kito, Yokohama, JP;
Nobutoshi Aoki, Yokohama, JP;
Masaru Kidoh, Kawasaki, JP;
Ryota Katsumata, Yokohama, JP;
Masaki Kondo, Yokohama, JP;
Naoki Kusunoki, Yokohama, JP;
Toshiyuki Enda, Zushi, JP;
Sanae Ito, Yokohama, JP;
Hiroyoshi Tanimoto, Yokohama, JP;
Hideaki Aochi, Kawasaki, JP;
Akihiro Nitayama, Yokohama, JP;
Riichiro Shirota, Fujisawa, JP;
Masaru Kito, Yokohama, JP;
Nobutoshi Aoki, Yokohama, JP;
Masaru Kidoh, Kawasaki, JP;
Ryota Katsumata, Yokohama, JP;
Masaki Kondo, Yokohama, JP;
Naoki Kusunoki, Yokohama, JP;
Toshiyuki Enda, Zushi, JP;
Sanae Ito, Yokohama, JP;
Hiroyoshi Tanimoto, Yokohama, JP;
Hideaki Aochi, Kawasaki, JP;
Akihiro Nitayama, Yokohama, JP;
Riichiro Shirota, Fujisawa, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.