The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 2010
Filed:
May. 03, 2007
Belgacem Haba, Saratoga, CA (US);
Masud Beroz, Cary, NC (US);
Teck-gyu Kang, San Jose, CA (US);
Yoichi Kubota, Pleasanton, CA (US);
Sridhar Krishnan, San Francisco, CA (US);
John B. Riley, Iii, Dallas, TX (US);
Ilyas Mohammed, Santa Clara, CA (US);
Belgacem Haba, Saratoga, CA (US);
Masud Beroz, Cary, NC (US);
Teck-Gyu Kang, San Jose, CA (US);
Yoichi Kubota, Pleasanton, CA (US);
Sridhar Krishnan, San Francisco, CA (US);
John B. Riley, III, Dallas, TX (US);
Ilyas Mohammed, Santa Clara, CA (US);
Tessera, Inc., San Jose, CA (US);
Abstract
A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.