The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2010

Filed:

May. 15, 2006
Applicants:

Rajendra D. Pendse, Fremont, CA (US);

Marcos Karnezos, Palo Alto, CA (US);

Kyung-moon Kim, Ichon-si, KR;

Koo Hong Lee, Seoul, KR;

Moon Hee Lee, Ichon-si, KR;

Orion Starr, San Jose, CA (US);

Inventors:

Rajendra D. Pendse, Fremont, CA (US);

Marcos Karnezos, Palo Alto, CA (US);

Kyung-Moon Kim, Ichon-si, KR;

Koo Hong Lee, Seoul, KR;

Moon Hee Lee, Ichon-si, KR;

Orion Starr, San Jose, CA (US);

Assignee:

STATS ChipPAC, Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods for forming flip chip interconnection, in which the bump interconnect is defined at least in part by an underfill. The underfill includes a material that is thermally cured; that is, raising the temperature of the underfill material can result in progressive curing of the underfill through stages including a gel stage and a fully cured stage. According to the invention, during at least an early stage in the process the semiconductor chip is carried by a thermode, which is employed to control the temperature of the assembly in a specified way. Also, flip chip interconnections and flip chip packages made according to the methods of invention.


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