The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 2010
Filed:
Jan. 11, 2008
Dureseti Chidambarrao, Weston, CT (US);
Ying LI, Newburgh, NY (US);
Rajeev Malik, Pleasantville, NY (US);
Shreesh Narasimha, Beacon, NY (US);
Haining Yang, Wappingers Fall, NY (US);
Huilong Zhu, Poughkeepsie, NY (US);
Dureseti Chidambarrao, Weston, CT (US);
Ying Li, Newburgh, NY (US);
Rajeev Malik, Pleasantville, NY (US);
Shreesh Narasimha, Beacon, NY (US);
Haining Yang, Wappingers Fall, NY (US);
Huilong Zhu, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.