The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2010
Filed:
Oct. 26, 2007
Salman Akram, Boise, ID (US);
Charles M. Watkins, Eagle, ID (US);
William M. Hiatt, Eagle, ID (US);
David R. Hembree, Boise, ID (US);
James M. Wark, Boise, ID (US);
Warren M. Farnworth, Nampa, ID (US);
Mark E. Tuttle, Boise, ID (US);
Sidney B. Rigg, Meridian, ID (US);
Steven D. Oliver, Boise, ID (US);
Kyle K. Kirby, Eagle, ID (US);
Alan G. Wood, Boise, ID (US);
LU Velicky, Boise, ID (US);
Salman Akram, Boise, ID (US);
Charles M. Watkins, Eagle, ID (US);
William M. Hiatt, Eagle, ID (US);
David R. Hembree, Boise, ID (US);
James M. Wark, Boise, ID (US);
Warren M. Farnworth, Nampa, ID (US);
Mark E. Tuttle, Boise, ID (US);
Sidney B. Rigg, Meridian, ID (US);
Steven D. Oliver, Boise, ID (US);
Kyle K. Kirby, Eagle, ID (US);
Alan G. Wood, Boise, ID (US);
Lu Velicky, Boise, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.