The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2010

Filed:

May. 27, 2008
Applicants:

Naofumi Ohashi, Hannou, JP;

Junji Noguchi, Ome, JP;

Toshinori Imai, Ome, JP;

Hizuru Yamaguchi, Akishima, JP;

Nobuo Owada, Ome, JP;

Kenji Hinode, Hachiouji, JP;

Yoshio Homma, Hinode-machi, JP;

Seiichi Kondo, Kokubunji, JP;

Inventors:

Naofumi Ohashi, Hannou, JP;

Junji Noguchi, Ome, JP;

Toshinori Imai, Ome, JP;

Hizuru Yamaguchi, Akishima, JP;

Nobuo Owada, Ome, JP;

Kenji Hinode, Hachiouji, JP;

Yoshio Homma, Hinode-machi, JP;

Seiichi Kondo, Kokubunji, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.


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