The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 2010
Filed:
Oct. 20, 2006
Hsiang-ming Huang, Tainan, TW;
An-hong Liu, Tainan, TW;
Yeong-jyh Lin, Tainan, TW;
Yi-chang Lee, Tainan, TW;
Hsiang-Ming Huang, Tainan, TW;
An-Hong Liu, Tainan, TW;
Yeong-Jyh Lin, Tainan, TW;
Yi-Chang Lee, Tainan, TW;
ChipMos Technologies Inc., Hsinchu, TW;
ChipMos Technologies (Bermuda) Ltd., Hamilton, BM;
Abstract
An IC package to enhance the bondibility of embedded bumps, primarily includes a substrate having a plurality of bump-accommodating holes, a bumped chip, an encapsulant, and a plurality of external terminals. The substrate further has a plurality of inner pads at one ends of the bump-accommodating holes respectively. The inner pads may be meshed or a soldering layer is disposed thereon for improving bump connection. The chip is attached to the substrate with the bumps aligned and embedded in the corresponding bump-accommodating holes. The encapsulant is at least formed on a lower surface of the substrate to encapsulate the meshes or the soldering layer. By the suspended meshes or/and the soldering layer, the bumps can be easily bonded at lower temperatures to simplify the manufacturing process with shorter electrical conductive paths and thinner package profiles without wire sweeping.