The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 17, 2009
Filed:
Aug. 07, 2008
Hiroyuki Tenmei, Odawara, JP;
Kunihiko Nishi, Kokubunji, JP;
Yasuhiro Naka, Hitachinaka, JP;
Nae Hisano, Matsudo, JP;
Hiroaki Ikeda, Hachioji, JP;
Masakazu Ishino, Yokohama, JP;
Hiroyuki Tenmei, Odawara, JP;
Kunihiko Nishi, Kokubunji, JP;
Yasuhiro Naka, Hitachinaka, JP;
Nae Hisano, Matsudo, JP;
Hiroaki Ikeda, Hachioji, JP;
Masakazu Ishino, Yokohama, JP;
Elpida Memory, Inc., Tokyo, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the principal surfaces. However, there is a problem of poor electrical coupling due to displacement of the bumps and the pads when bonded together. The present invention solves such a problem by conducting temporary positioning of the silicon wafers, adjusting the positions of the coupling bumps and pads while confirming the positions by a method such as x-ray capable of passing through the silicon wafers, and bonding the bumps and the pads together while hardening an interlayer adhesive provided between the principal surfaces of the silicon wafers by thermocompression.