The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2009

Filed:

Sep. 27, 2006
Applicants:

Sarah E. Kim, Portland, OR (US);

R. Scott List, Beaverton, OR (US);

Tom Letson, Beaverton, OR (US);

Inventors:

Sarah E. Kim, Portland, OR (US);

R. Scott List, Beaverton, OR (US);

Tom Letson, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/30 (2006.01); H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.


Find Patent Forward Citations

Loading…