The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 2009
Filed:
Jan. 25, 2007
Hongning Yang, Chandler, AZ (US);
Veronique C. Macary, Chandler, AZ (US);
Won Gi Min, Chandler, AZ (US);
Jiang-kai Zuo, Chandler, AZ (US);
Hongning Yang, Chandler, AZ (US);
Veronique C. Macary, Chandler, AZ (US);
Won Gi Min, Chandler, AZ (US);
Jiang-Kai Zuo, Chandler, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An N-channel device () is described having a lightly doped substrate (') in which adjacent or spaced-apart P (′) and N () wells are provided. A lateral isolation wall () surrounds at least a portion of the substrate (′) and is spaced apart from the wells (). A first gate (G) () overlies the P () well or the substrate (′) between the wells () or partly both. A second gate (G) (), spaced apart from G(), overlies the N-well (). A body contact () to the substrate (′) is spaced apart from the isolation wall () by a first distance () within the space charge region of the substrate (′) to isolation wall () PN junction. When the body contact () is connected to G(), a predetermined static bias Vgis provided to G() depending upon the isolation wall bias (Vbias) and the first distance (). The resulting device () operates at higher voltage with lower Rdson and less HCI.