The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2009

Filed:

Dec. 28, 2006
Applicants:

Ming Shiang Chen, Hsinchu, TW;

Wen Pin LU, Hsinchu, TW;

I-jen Huang, Kaohsiung, TW;

Chi Yuan Chin, Taipei, TW;

Nian-kai Zous, Ping Zhen, TW;

Inventors:

Ming Shiang Chen, Hsinchu, TW;

Wen Pin Lu, Hsinchu, TW;

I-Jen Huang, Kaohsiung, TW;

Chi Yuan Chin, Taipei, TW;

Nian-Kai Zous, Ping Zhen, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods for programming and program verification of a flash memory are described that ease the buried drain contact induced operation and increase the retention window. In a first aspect of the invention, a program operation method provides varying program biases which are applied to different groups of memory cells. The program biases can be supplied as drain bias voltages or gate bias voltages. The program biases vary depending on which group of memory cells is programmed. In one embodiment, a first drain voltage Vis applied to the first group of memory cells Mand M. A second drain voltage Vis applied to the second group of memory cells Mand M, where V=V+ΔV. In a second aspect of the invention, a plurality of program verification voltage levels are selected to verify that the memory cells pass the program voltage levels.


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