The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2009
Filed:
Apr. 09, 2007
Clinton Chao, Hsinchu, TW;
Louis Liu, Hsin-Chu, TW;
Lewis Chu, Pingjhen, TW;
Mark Shane Peng, Hsinchu, TW;
Chao-shun Hsu, Sansing Township, Yilan County, TW;
Kim Chen, Fremont, CA (US);
Clinton Chao, Hsinchu, TW;
Louis Liu, Hsin-Chu, TW;
Lewis Chu, Pingjhen, TW;
Mark Shane Peng, Hsinchu, TW;
Chao-Shun Hsu, Sansing Township, Yilan County, TW;
Kim Chen, Fremont, CA (US);
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
SiP design systems and methods. The system comprises a system partitioning module, a subsystem integration module, a physical design module, and an analysis module. The system partitioning module partitions a target system into subsystem partitions according to partition criteria. The subsystem integration module generates an architecture design and/or a cost estimation for the target system according to the subsystem partitions, at least one SiP platform, and IC geometry data. The physical design module generates a SiP physical design with physical routing for the target system according to the architecture design, the subsystem partitions, the SiP platform, and the IC geometry data. The analysis module performs a performance check within the subsystem partitions based on the SiP physical design and/or simulations of the target system.