The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2009
Filed:
Sep. 23, 2005
Jae-hwa Park, Gyeonggi-do, KR;
Gil-heyun Choi, Gyeonggi-do, KR;
Chang-won Lee, Gyeonggi-do, KR;
Byung-hak Lee, Suwon-si, KR;
Hee-sook Park, Seoul, KR;
Woong-hee Sohn, Gyeonggi-do, KR;
Jong-ryeol Yoo, Gyeonggi-do, KR;
Sun-pil Yun, Seoul, KR;
Jang-hee Lee, Seoul, KR;
Dong-chan Lim, Seoul, KR;
Jae-Hwa Park, Gyeonggi-do, KR;
Gil-Heyun Choi, Gyeonggi-do, KR;
Chang-Won Lee, Gyeonggi-do, KR;
Byung-Hak Lee, Suwon-si, KR;
Hee-Sook Park, Seoul, KR;
Woong-Hee Sohn, Gyeonggi-do, KR;
Jong-Ryeol Yoo, Gyeonggi-do, KR;
Sun-Pil Yun, Seoul, KR;
Jang-Hee Lee, Seoul, KR;
Dong-Chan Lim, Seoul, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
Embodiments of the present invention include semiconductor devices that can be made with relatively low resistance, and methods of forming the semiconductor devices. A resistance reducing layer is formed between a polysilicon layer and a metal layer. As a result, an interface resistance between the polysilicon layer and the metal layer is greatly reduced and a distribution of the interface resistance is very uniform. As a result, a conductive structure including the resistance reducing layer has a greatly reduced sheet resistance to improve electrical characteristics of a semiconductor device having the conductive structure.