The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2009
Filed:
Aug. 30, 2005
Sangwoo Pae, Beaverton, OR (US);
Jose Maiz, Portland, OR (US);
Justin Brask, Portland, OR (US);
Gilbert Dewey, Hillsboro, OR (US);
Jack Kavalieros, Portland, OR (US);
Robert Chau, Beaverton, OR (US);
Suman Datta, Beaverton, OR (US);
Sangwoo Pae, Beaverton, OR (US);
Jose Maiz, Portland, OR (US);
Justin Brask, Portland, OR (US);
Gilbert Dewey, Hillsboro, OR (US);
Jack Kavalieros, Portland, OR (US);
Robert Chau, Beaverton, OR (US);
Suman Datta, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 Å to 60 Å. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600° C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack.