The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2009
Filed:
Jun. 07, 2005
Soon-bum Kim, Suwon-si, KR;
Ung-kwang Kim, Yongin-si, KR;
Keum-hee MA, Andong-si, KR;
Young-hee Song, Yongin-si, KR;
Sung-min Sim, Seongnam-si, KR;
Se-yong OH, Yongin-si, KR;
Kang-wook Lee, Suwon-si, KR;
Se-young Jeong, Seoul, KR;
Soon-Bum Kim, Suwon-si, KR;
Ung-Kwang Kim, Yongin-si, KR;
Keum-Hee Ma, Andong-si, KR;
Young-Hee Song, Yongin-si, KR;
Sung-Min Sim, Seongnam-si, KR;
Se-Yong Oh, Yongin-si, KR;
Kang-Wook Lee, Suwon-si, KR;
Se-Young Jeong, Seoul, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
A method of fabricating wafer level chip scale packages may involve forming a hole to penetrate through a chip pad of an IC chip. A base metal layer may be formed on a first face of a wafer to cover inner surfaces of the hole. An electrode metal layer may fill the hole and rise over the chip pad. A second face of the wafer may be grinded such that the electrode metal layer in the hole may be exposed through the second face. By electroplating, a plated bump may be formed on the electrode metal layer exposed through the second face. The base metal layer may be selectively removed to isolate adjacent electrode metal layers. The wafer may be sawed along scribe lanes to separate individual packages from the wafer.