The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2009

Filed:

Mar. 23, 2006
Applicants:

Scott N. Gatzemeier, Boise, ID (US);

Joemar D. Sinipete, Boise, ID (US);

Robert J. Ringhofer, Boise, ID (US);

Nevil Gajera, Boise, ID (US);

Mark A. Hawes, Boise, ID (US);

Inventors:

Scott N. Gatzemeier, Boise, ID (US);

Joemar D. Sinipete, Boise, ID (US);

Robert J. Ringhofer, Boise, ID (US);

Nevil Gajera, Boise, ID (US);

Mark A. Hawes, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 27/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and structures are described to provide trims for die on a wafer. The trims are set on a die-by-die basis instead of a wafer basis. Accordingly, the individual die are more finely tuned and more die operate at the target specifications so that yield is increased. In an embodiment, the odd and even blocks of each non volatile memory die are erased and then programmed to test the program time. Statistical analysis of the tested program times is performed. Based on this analysis the trim values are determined and programmed into the die. Accordingly, each die on a wafer has its individual trim settings.


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