The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2009
Filed:
Oct. 12, 2005
Tadahiro Kato, Fukushima, JP;
Masayoshi Sekizawa, Niigata, JP;
Mamoru Okada, Nagano, JP;
Hisashi Kijima, Gunma, JP;
Tadahiro Kato, Fukushima, JP;
Masayoshi Sekizawa, Niigata, JP;
Mamoru Okada, Nagano, JP;
Hisashi Kijima, Gunma, JP;
Shin-Etsu Handotai Co., Ltd., Tokyo, JP;
Abstract
The present invention is a method for producing a semiconductor wafer, comprising: at least a double-side polishing step; and a chamfered-portion polishing step; wherein as a first chamfered-portion polishing step, at least, a chamfered portion of the wafer is polished so that a chamfered surface of each of main surface sides in the chamfered portion is in contact with a polishing pad; then the double-side polishing is performed; as a second chamfered-portion polishing step, at least, the chamfered portion of the wafer is polished so that an end surface of the chamfered portion is in contact with a polishing pad and so that both main surfaces of the wafer are not in contact with a polishing pad. Thereby, when a semiconductor wafer is produced, scratch and such generated in the chamfered portion in a double-side polishing process can be removed and, excessive polishing in a peripheral portion of a main surface can be prevented from being caused in polishing a chamfered portion. Therefore, a method for producing a semiconductor wafer having a high flatness even in the vicinity of a chamfered portion, and the semiconductor wafer are provided.