The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2009
Filed:
May. 19, 2006
Robert J. Purtell, Mohegan Lake, NY (US);
Henry K. Utomo, Newburgh, NY (US);
Yun-yu Wang, Poughquag, NY (US);
Haining S. Yang, Wappingers Falls, NY (US);
Robert J. Purtell, Mohegan Lake, NY (US);
Henry K. Utomo, Newburgh, NY (US);
Yun-Yu Wang, Poughquag, NY (US);
Haining S. Yang, Wappingers Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention provides a method of fabricating semiconductor device comprising at least one field effect transistor (FET) having source and drain (S/D) metal silicide layers with intrinsic tensile or compressive stress. First, a metal layer containing a silicide metal M is formed over S/D regions of a FET, followed by a first annealing step to form S/D metal silicide layers that comprise a metal silicide of a first phase (MSi). A silicon nitride layer is then formed over the FET, followed by a second annealing step. During the second annealing step, the metal silicide is converted from the first phase (MSi) into a second phase (MSi) with x<y. The metal silicide conversion causes either volumetric shrinkage or expansion in the S/D metal silicide layers of the FET, which in turn generates intrinsic tensile or compressive stress in the S/D metal silicide layers under confinement by the silicon nitride layer.